The present application relates to semiconductor technology, and more particularly to a replacement gate FinFET manufacturing process in which the source/drain regions, gate structure and gate spacer are all defined by utilizing a single sidewall image transfer technique. The present application also provides a semiconductor structure, i.e., replacement gate FinFET structure, that is provided by the method of the present application.
For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continue scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that MOSFETs are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, further methods for improving performance in addition to scaling have become critical.
The use of non-planar semiconductor devices such as, for example, semiconductor fin field effect transistors (FinFETs), is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices. Semiconductor FinFETs can achieve higher drive currents with increasingly smaller dimensions as compared to conventional planar FETs.
In prior art replacement gate FinFET manufacturing processes, the integration process typically includes (1) forming a semiconductor fin, (2) forming a sacrificial gate structure, (3) forming a spacer, (4) forming source/drain regions, (5) replacing the sacrificial gate structure with a permanent, i.e., functional, gate structure, and (6) forming self-aligned contacts to the source/drain regions.
Such prior art replacement gate FinFET manufacturing processes are complicated and gate critical dimension variation and contact to gate overlay error may reduce the space for the contact area. Furthermore, the sacrificial gate and spacer etching steps add more process implications of semiconductor fin erosion and damage which, in turn, may cause problems in forming epitaxially merged source/drain structures. Additionally, the spacer etch may result in insufficient spacer removal between the semiconductor fins, which may cause semiconductor fin epitaxy merge concerns. Furthermore, the spacer etch may expose the top corners of the sacrificial gate structure which may result in nodules being formed during the formation of merged epitaxial source/drain regions.
There is thus a need for providing a new replacement gate FinFET manufacturing process that overcomes or at least suppresses the problems mentioned above with prior art replacement gate FinFET manufacturing processes.